High-frequency circuits in BIPOLAR, BICMOS and CMOS technology require integrated capacitors with a high voltage linearity, accurately settable capacitances and in particular low parasitic capacitances. The conventional MOS or MIS capacitors which have been used hitherto have an unsatisfactory voltage linearity on account of voltage-induced space charge regions. The short distance from the substrate also entails numerous parasitic capacitances.
These difficulties can be avoided by using what are known as metal-insulator-metal capacitors (MIM capacitors), which are usually arranged between two metallization levels and are therefore at a considerably greater distance from the substrate. As far as possible, these metal-insulator-metal capacitors should be integrated in the existing concepts for multilayer metallization without changing and influencing the adjacent interconnects.
Modern multilayer metallizations are preferably fabricated using the “Damascene” process. In this process, the structures for future interconnects or vias are etched into the intermetal dielectric. Then, these structures are filled with the interconnect material (e.g. copper). The metal remaining on the surface is then removed again in a final chemical mechanical polishing (CMP) step. One advantage of the “Damascene” technique is that it can be used even for very small feature sizes for which reactive ion etching (RIE) can no longer be used. Furthermore, the “Damascene” technique is also suitable for all metals which, for example like copper, do not form any highly volatile compounds and therefore cannot be patterned by means of RIE processes.
Previous approaches, such as for example those which are known from the European patent application EP 1 130 654 A1 and the articles “Single Mask MIM Capacitor with Cu Damascene Metallization for sub-0.18 μm Mixed Mode Signal and System-on-a-Chip Applications”, IEEE (2000), pp. 111 ff. by Kiu et al. and “System on a Chip Technology Platform for 0.18 μm Digital, Mixed Signal & eDRAM Applications”, Infineon Techn. Corp. and IBM Michroelectronics Div. by R. Mahnkopf et al., use the materials silicon dioxide and/or silicon nitride, which are well characterized and known in the microelectronics industry, as dielectrics.
However, the dielectric constants k of these materials are not especially high, at approximately four to seven. Furthermore, on account of the use in the multilayer metallization, they have to be deposited using plasma (PECVD) processes. These processes are typically distinguished by high deposition rates, but also by high defect densities and lower layer qualities. Therefore, in plasma processes it is virtually impossible to produce layers of less than 60 nm with a reproducible thickness and sufficient quality.
Moreover, in the integration concepts cited above, the top electrode is patterned with the aid of a top electrode etch, which has to be stopped in the dielectric of the capacitor. For this reason, these processes absolutely must have a dielectric layer with a sufficient thickness of at least 60 nm.
FIG. 4 shows an excerpt from a cross section through an integrated semiconductor product having an MIM capacitor according to the prior art. In a lower intermetal dielectric 1, lower interconnects 20 are connected by means of vias 21 to a middle level of interconnects 3, 19. The interconnects 3, 19, 20 and the vias 21 are fabricated by means of the “Damascene” technique.
Then, a 50 nm thick layer of TaN is applied by means of PVD deposition, as lower electrode 2 of the capacitor, to the planarized surface of the middle interconnect level. A layer which is once again approx. 60 nm thick is then applied as capacitor dielectric 6 to the layer of TaN. This layer 6 may, for example, consist of SiO2 which is deposited by means of CVD. Above this, the second electrode 8 of the capacitor is applied; it may be formed, for example, by a 50 nm thick TaN layer.
This is followed by the patterning of the layer stack which is intended to form the capacitor, the etching stop in the region of the capacitor (on the left-hand side of the figure) having to take place on the intermetal dielectric, while the etching stop in the region of the central interconnect 3 takes place on copper. After the patterning, a passivation layer 12 of Si3N4 is deposited. Vias 13 are used to make contact with the central interconnect 3 and the upper electrode 8 of the capacitor. These vias 13 are formed in an upper intermetal dielectric 11 and are closed off by upper interconnects 14. The surface formed in this way is once again planarized by means of CMP.
In particular the required etching stop on copper and the subsequent removal of resist with uncovered copper cause considerable process engineering difficulties.
There is a considerable risk of the quality of the copper track 3 being adversely affected. A further problem is caused by the capacitor stack 2, 6, 8 being completely etched clear. Undercut etching results in an increased likelihood of failure being caused by possible short circuits at the vertical edges.
The problem of the etching stop on copper has already been recognized in the prior art. According to a solution which is already known, it is proposed for a thin layer of Si3N4 to additionally be deposited immediately after the planarization of the central interconnect level 1, 3, 19. Then, the Si3N4 layer is opened up at the location at which the MIM capacitor is provided. The photoresist required for this step is stripped with the copper track 19 uncovered, (left-hand side of FIG. 4).
With the process described above, the process engineering problem arises that when opening up the Si3N4 layer, the photoresist has to be removed with the copper track uncovered. Since copper is susceptible to oxidation, therefore, it is necessary to reckon with a deterioration in the interconnect quality. Moreover, an additional patterning step and also an additional photomask are required compared to the process which was outlined first, and this in turn significantly increases the effort and cost involved in the process sequence.
In the integrated semiconductor product described in EP 1 130 654 A1, the existing copper track 19 is used as lower electrode 2. A layer stack comprising capacitor dielectric and the material for the upper electrode 8 is deposited on the surface which has been planarized by means of CMP technology. Then, this stack is patterned, it being necessary for the etching operation to be stopped in the capacitor dielectric 6.
Since in this method the etching operation has to stop in the capacitor dielectric, there are strict limits with regard to the thickness and the capacitor material used for the dielectric 6. Since, moreover, the dielectric is deposited directly on the extremely sensitive copper surface, the susceptibility of copper to oxidation means that plasma processes which use oxygen as a reaction partner cannot be used to deposit SiO2. Consequently, SiO2 and other oxygen-containing materials cannot be used as capacitor dielectrics in this process.
Furthermore, the surface area-specific capacitance of known capacitors of this type is around 1 fF/μm2; however, for future high-frequency applications, a multiple of this capacitance will be required. The surface area-specific capacitance of a capacitor is substantially determined by the thickness of the dielectric separating layer and the dielectric constant. Therefore, the surface area-specific capacitance of a capacitor can be increased by using dielectrics with a high dielectric constant (>8). Furthermore, insulation layers which are thinner than 60 nm lead to an increase in the surface area-specific capacitance.